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ICS
2009
Tsinghua U.
16 years 1 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron
LCPC
2005
Springer
15 years 12 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...
PACS
2004
Springer
146views Hardware» more  PACS 2004»
15 years 11 months ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...
DEBU
2008
125views more  DEBU 2008»
15 years 6 months ago
Querying XML in Timber
In this paper, we describe the TIMBER XML database system implemented at University of Michigan. TIMBER was one of the first native XML database systems, designed from the ground ...
Yuqing Wu, Stelios Paparizos, H. V. Jagadish
ICIP
2005
IEEE
16 years 8 months ago
A reconfigurable multi-camera architecture for high resolution objects analysis
In this paper, a multi-camera architecture is presented for heterogeneous targets analysis and tracking. The proposed system can be switched in various configurations enabling aut...
Luca Marchesotti, Stefano Piva, Andrea F. Cattoni,...