3120 search results - page 137 / 624 » An optimal architecture for a DDC |
179
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EUROPAR
2001
Springer
15 years 11 months ago
2001
Springer
Abstract. This paper describes a software architecture that allows image processing researchers to develop parallel applications in a transparent manner. The architecture’s main ...
172
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ICIP
2009
IEEE
16 years 7 months ago
2009
IEEE
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
191
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FECS
2010
15 years 4 months ago
2010
In this paper, we present a method to help teach computer architecture (or computer organization) by developing an in class system where the students, themselves, compile high-leve...
162
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
In this paper, we investigate the core-switch mapping(CSM) problem that optimally maps cores onto an NoC architecture such that either the energy consumption or the congestion is ...
172
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GLOBECOM
2007
IEEE
16 years 24 days ago
2007
IEEE
— Relay networks have received considerable attention recently, especially when limited size and power resources impose constraints on the number of antennas within a wireless se...