3120 search results - page 130 / 624 » An optimal architecture for a DDC |
135
click to vote
EUROPAR
2004
Springer
15 years 11 months ago
2004
Springer
Abstract. The features of the IA64 architecture create new opportunities for link-time optimization. At the same time they complicate the design of a link-time optimizer. This pape...
190
click to vote
VLSID
2007
IEEE
16 years 6 months ago
2007
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
157
click to vote
DAC
2005
ACM
16 years 7 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
185
click to vote
SAMOS
2007
Springer
16 years 16 days ago
2007
Springer
This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on...
161
click to vote
IFIP
1994
Springer
15 years 10 months ago
1994
Springer
We describe the architecture of an evolving algebra partial evaluator, a program which specializes an evolving algebra with respect to a portion of its input. We discuss the parti...