3120 search results - page 120 / 624 » An optimal architecture for a DDC |
141
click to vote
EUROPAR
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. We present a hardware mechanism which dynamically detects uniform and affine vectors used in Graphics Processing Units, to minimize pressure on the register file and redu...
187
click to vote
DAC
1997
ACM
15 years 10 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
171
click to vote
DAC
2008
ACM
15 years 8 months ago
2008
ACM
level of accuracy in IC package abstraction (compact models) to ensure robust thermal design. An overarching goal must be to reduce power consumption per function through smart pro...
131
click to vote
CCE
2006
15 years 6 months ago
2006
The regulatory architecture responsible for robust maintenance of 24 h cycles is analyzed as a control system. At the gene regulatory level, it is shown that performance attribute...
201
click to vote
DAC
2012
ACM
13 years 8 months ago
2012
ACM
In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput f...