3120 search results - page 105 / 624 » An optimal architecture for a DDC |
166
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IPPS
1998
IEEE
15 years 10 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
164
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SIGGRAPH
1994
ACM
15 years 10 months ago
1994
ACM
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
156
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ETS
2007
IEEE
15 years 8 months ago
2007
IEEE
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
186
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ICMCS
2010
IEEE
15 years 7 months ago
2010
IEEE
The increasingly large amount of digital multimedia content has created a need for technologies to search and identify multimedia files. Multimedia fingerprinting has been widely ...
145
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ENGL
2008
15 years 6 months ago
2008
Abstract--Over-sampling sigma-delta analog-todigital converters (ADCs) are one of the key building blocks of state of the art wireless transceivers. In sigma-delta modulator design...