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ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
14 years 2 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang
ICESS
2007
Springer
16 years 20 days ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam
CVPR
2009
IEEE
17 years 1 months ago
Vocabulary Hierarchy Optimization for Effective and Transferable Retrieval
Scalable image retrieval systems usually involve hierarchical quantization of local image descriptors, which produces a visual vocabulary for inverted indexing of images. Although ...
Rongrong Ji (Harbin Institute of Technology), Xing...
CIDM
2009
IEEE
16 years 1 months ago
Ensemble member selection using multi-objective optimization
— Both theory and a wealth of empirical studies have established that ensembles are more accurate than single predictive models. Unfortunately, the problem of how to maximize ens...
Tuve Löfström, Ulf Johansson, Henrik Bos...
IJCV
2000
164views more  IJCV 2000»
15 years 6 months ago
Probabilistic Modeling and Recognition of 3-D Objects
This paper introduces a uniform statistical framework for both 3-D and 2-D object recognition using intensity images as input data. The theoretical part provides a mathematical too...
Joachim Hornegger, Heinrich Niemann