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» An interconnection architecture for micropayment systems
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NOCS
2007
IEEE
16 years 13 days ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
16 years 4 days ago
Physical design implementation of segmented buses to reduce communication energy
Abstract— The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, ...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
FPGA
1995
ACM
142views FPGA» more  FPGA 1995»
15 years 9 months ago
The Design of RPM: An FPGA-based Multiprocessor Emulator
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improveme...
Koray Öner, Luiz André Barroso, Sasan ...
IPPS
1998
IEEE
15 years 10 months ago
Failure Recovery for Distributed Processes in Single System Image Clusters
Single System Image (SSI) Distributed Operating Systems have been the subject of increasing interest in recent years. This interest has been fueled primarily by the trend towards ...
Jeffrey Zabarsky
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
16 years 13 days ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...