443 search results - page 54 / 89 » An interconnection architecture for micropayment systems |
157
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ISCA
2008
IEEE
16 years 16 days ago
2008
IEEE
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
173
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AINA
2009
IEEE
16 years 29 days ago
2009
IEEE
Networking infrastructure is a vital part of virtual computer clusters. This paper describes VirtCloud, a system for interconnecting virtual clusters in a state-wide network based...
150
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DATE
2006
IEEE
16 years 6 days ago
2006
IEEE
Verification quality is a must for functional safety in electronic systems. In automotive, the verification flow is historically based on a layered approach, where each level (mod...
195
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JSA
2010
15 years 28 days ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
174
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VLSID
2006
IEEE
16 years 4 days ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...