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JUCS
2006
112views more  JUCS 2006»
15 years 6 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
PPL
2008
185views more  PPL 2008»
15 years 6 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ET
2007
101views more  ET 2007»
15 years 6 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
HIPEAC
2005
Springer
15 years 11 months ago
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
Pedro Javier García, Jose Flich, José...
PDP
2009
IEEE
16 years 28 days ago
Phoenix: A Runtime Environment for High Performance Computing on Chip Multiprocessors
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
Avneesh Pant, Hassan Jafri, Volodymyr V. Kindraten...