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» An improvement in formal verification
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TCAD
2002
121views more  TCAD 2002»
15 years 6 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
ESORICS
2008
Springer
15 years 8 months ago
Symmetric Key Approaches to Securing BGP - A Little Bit Trust Is Enough
The Border Gateway Protocol (BGP) is the de facto inter-domain routing protocol that connects autonomous systems (ASes). Despite its importance for the Internet infrastructure, BGP...
Bezawada Bruhadeshwar, Sandeep S. Kulkarni, Alex X...
POPL
2010
ACM
16 years 3 months ago
From Program Verification to Program Synthesis
This paper describes a novel technique for the synthesis of imperative programs. Automated program synthesis has the potential to make programming and the design of systems easier...
Saurabh Srivastava, Sumit Gulwani, Jeffrey S. Fost...
SEW
2003
IEEE
15 years 11 months ago
Instrumentation of Intermediate Code for Runtime Verification
Runtime monitoring is aimed at ensuring correct runtime behavior with respect to specified constraints. It provides assurance that properties are maintained during a given program...
Ann Q. Gates, Oscar Mondragon, Mary Payne, Steve R...
ICCTA
2007
IEEE
15 years 10 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...