75 search results - page 3 / 15 » An efficient approach to simultaneous transistor and interco... |
123
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
— Circuit placement has a large impact on all aspects of performance; speed, power consumption, reliability, and cost are all affected by the physical locations of interconnected...
149
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ISPD
2000
ACM
15 years 10 months ago
2000
ACM
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...
181
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TCAD
2008
15 years 5 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
115
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ICCD
2006
IEEE
16 years 2 months ago
2006
IEEE
— Continued scaling of CMOS has lead to a problem of scale as gates are faster than light travelling across a chip. Scalability used to be the hallmark of CMOS. Half the size, do...
157
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JMLR
2010
15 years 23 days ago
2010
We propose a novel application of the Simultaneous Orthogonal Matching Pursuit (SOMP) procedure to perform variable selection in ultra-high dimensional multiple output regression ...