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JCP
2007
94views more  JCP 2007»
15 years 5 months ago
Low-Complexity Analysis of Repetitive Regularities for Biometric Applications
— Presented in this paper is a joint algorithm optimization and architecture design framework for analysis of repetitive regularities. Two closely coupled algorithm optimization ...
Lei Wang, Niral Patel
PLDI
1994
ACM
15 years 10 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
ISPDC
2010
IEEE
15 years 4 months ago
Resource-Aware Compiler Prefetching for Many-Cores
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
George C. Caragea, Alexandros Tzannes, Fuat Keceli...
ISSS
1999
IEEE
126views Hardware» more  ISSS 1999»
15 years 10 months ago
Catalyst: A DSIP Design Flow Development in Industry
The Motorola System on Chip Design Technologies (SoCDT) team aims at providing a system design environment for its customers. The Toulouse branch concentrates on design efforts in...
W. De Rammelaere, K. Eckert, T. Lawell, R. McGarit...
CONEXT
2007
ACM
15 years 10 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure