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ICASSP
2008
IEEE
16 years 1 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
NOCS
2007
IEEE
16 years 29 days ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
235
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ATAL
2007
Springer
16 years 26 days ago
A framework for agent-based distributed machine learning and data mining
This paper proposes a framework for agent-based distributed machine learning and data mining based on (i) the exchange of meta-level descriptions of individual learning processes ...
Jan Tozicka, Michael Rovatsos, Michal Pechoucek
FPL
2007
Springer
190views Hardware» more  FPL 2007»
16 years 25 days ago
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...
Andreas Herrholz, Frank Oppenheimer, Philipp A. Ha...
IPPS
2005
IEEE
16 years 8 days ago
WSPeer - An Interface to Web Service Hosting and Invocation
— This paper introduces WSPeer, a high level interface to hosting and invoking Web services. WSPeer aims to support the diversification of Web service deployments by providing a...
Andrew Harrison, Ian J. Taylor