4772 search results - page 61 / 955 » An approach to interface synthesis |
152
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VLSID
1997
IEEE
15 years 10 months ago
1997
IEEE
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
169
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CAV
2010
Springer
15 years 10 months ago
2010
Springer
Abstract. Synthesis of finite state systems from full linear time temporal logic (LTL) specifications is gaining more and more attention as several recent achievements have signi...
177
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DAC
2001
ACM
16 years 7 months ago
2001
ACM
We describe two things. First, we present a uniform framework for object oriented specification and verification of hardware. For this purpose the object oriented language `e'...
169
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
143
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APN
2007
Springer
16 years 15 days ago
2007
Springer
In this paper we develop a theory for the region-based synthesis of system models given as place/transition-nets with weighted inhibitor arcs (ptinets) from sets of scenarios descr...