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» An approach to interface synthesis
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DATE
2006
IEEE
142views Hardware» more  DATE 2006»
16 years 28 days ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ICPPW
2006
IEEE
16 years 27 days ago
Multidimensional Dataflow-based Parallelization for Multimedia Instruction Set Extensions
In retargeting loop-based code for multimedia instruction set extensions, a critical issue is that vector data types of mixed precision within a loop body complicate the paralleli...
Lewis B. Baumstark Jr., Linda M. Wills
CEC
2005
IEEE
16 years 15 days ago
Parallel evolutionary algorithms on graphics processing unit
Evolutionary Algorithms (EAs) are effective and robust methods for solving many practical problems such as feature selection, electrical circuits synthesis, and data mining. Howeve...
Man Leung Wong, Tien-Tsin Wong, Ka-Ling Fok
DATE
2003
IEEE
116views Hardware» more  DATE 2003»
16 years 5 days ago
Development and Application of Design Transformations in ForSyDe
The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstractio...
Ingo Sander, Axel Jantsch, Zhonghai Lu
ICCAD
1999
IEEE
119views Hardware» more  ICCAD 1999»
15 years 11 months ago
Factoring logic functions using graph partitioning
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
Martin Charles Golumbic, Aviad Mintz