4772 search results - page 315 / 955 » An approach to interface synthesis |
208
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
166
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
In this paper we propose an embedded software design flow, which starts from an UML model and provides automatic mapping to other models like Simulink or finite-state machines (FS...
217
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarante...
171
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ACSD
2005
IEEE
16 years 14 days ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
192
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ASPDAC
2004
ACM
16 years 8 days ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...