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» An approach to interface synthesis
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DATE
2010
IEEE
119views Hardware» more  DATE 2010»
15 years 11 months ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
ASPDAC
2007
ACM
129views Hardware» more  ASPDAC 2007»
15 years 10 months ago
ECO-system: Embracing the Change in Placement
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
Jarrod A. Roy, Igor L. Markov
LREC
2010
183views Education» more  LREC 2010»
15 years 8 months ago
AhoTransf: A Tool for Multiband Excitation Based Speech Analysis and Modification
In this paper we present AhoTransf, a tool that enables analysis, visualization, modification and synthesis of speech. AhoTransf integrates a speech signal analysis model with a g...
Ibon Saratxaga, Inmaculada Hernáez, Eva Nav...
FDL
2008
IEEE
16 years 1 months ago
Towards Compilation of Streaming Programs into FPGA Hardware
There is an increasing need for automated conversion of high-level design descriptions into hardware. We present a flow that converts a software application written in the Brook ...
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Br...
DSD
2007
IEEE
87views Hardware» more  DSD 2007»
16 years 1 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...