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ASPDAC
2009
ACM
127views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Timing driven power gating in high-level synthesis
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
Shih-Hsu Huang, Chun-Hua Cheng
VTS
2007
IEEE
135views Hardware» more  VTS 2007»
16 years 24 days ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
CGI
2006
IEEE
16 years 18 days ago
Appearance and Geometry Completion with Constrained Texture Synthesis
A novel approach for appearance and geometry completion over point-sampled geometry is presented in this paper. Based on the result of surface clustering and the given texture samp...
Chunxia Xiao, Wenting Zheng, Yongwei Miao, Yong Zh...
SI3D
2006
ACM
16 years 15 days ago
Hardware accelerated multi-resolution geometry synthesis
In this paper, we propose a new technique for hardware accelerated multi-resolution geometry synthesis. The level of detail for a given viewpoint is created on-the-fly, allowing f...
Martin Bokeloh, Michael Wand
LCTRTS
2001
Springer
15 years 11 months ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh