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TODAES
2008
115views more  TODAES 2008»
15 years 5 months ago
Automata-based assertion-checker synthesis of PSL properties
Abstract-- Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We ...
Marc Boule, Zeljko Zilic
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 10 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
DATE
2000
IEEE
124views Hardware» more  DATE 2000»
15 years 10 months ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
Christoph Scholl, Bernd Becker
MBUI
2004
104views User Interface» more  MBUI 2004»
15 years 7 months ago
An EUD Approach for Making MBUI Practical
In this paper, we present our perspective on Model-Based User Interfaces (hereafter MBUI) paradigm and provide with our experience in this area combining high-level knowledge-base...
José A. Macías, Pablo Castells
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
16 years 3 months ago
A Layout-Aware Synthesis Methodology for RF Circuits
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...