286 search results - page 28 / 58 » An analytical model for cache replacement policy performance |
141
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SRDS
2007
IEEE
16 years 13 days ago
2007
IEEE
The reliability of a large-scale storage system is influenced by a complex set of inter-dependent factors. This paper presents a comprehensive and extensible analytical framework ...
172
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USENIX
1994
15 years 7 months ago
1994
y-filled data block results in a delayed write,Abstract while a modification that fills a block results in an immediate, although asynchronous, write. TheSome file systems can dela...
145
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CASES
2001
ACM
15 years 9 months ago
2001
ACM
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...
151
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ICC
2007
IEEE
16 years 14 days ago
2007
IEEE
— In this paper, we present an analytic model and methodology to determine optimal scheduling policy that involves two dimension space allocation: time and code, in High Speed Do...
181
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JUCS
2000
15 years 6 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...