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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
16 years 3 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
CSCW
2010
ACM
16 years 3 months ago
Are you having difficulty?
It would be useful if software engineers/instructors could be aware that remote team members/students are having difficulty with their programming tasks. We have developed an appr...
Jason Carter, Prasun Dewan
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 3 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
EUROGRAPHICS
2010
Eurographics
16 years 1 months ago
Interactive High-Quality Visualization of Higher-Order Finite Elements
Higher-order finite element methods have emerged as an important discretization scheme for simulation. They are increasingly used in contemporary numerical solvers, generating a ...
Markus Üffinger, Steffen Frey, Thomas Ertl
MICCAI
2009
Springer
16 years 1 months ago
Multi-level Ground Glass Nodule Detection and Segmentation in CT Lung Images
Early detection of Ground Glass Nodule (GGN) in lung Computed Tomography (CT) images is important for lung cancer prognosis. Due to its indistinct boundaries, manual detection and ...
Yimo Tao, Le Lu, Maneesh Dewan, Albert Y. Chen, Ja...