Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a my...
Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Ra...
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...
The practical network performances of two commercial IEEE 802.11 compliant wireless local area networks (WLANs) are measured at the medium access control sublayer. A number of tes...
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
Safety of interoperation of program fragments written in different safe languages may fail when the languages have different systems of computational effects: an exception raised b...