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IJNS
2000
130views more  IJNS 2000»
15 years 6 months ago
A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems
An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach ...
Teresa Serrano-Gotarredona, Andreas G. Andreou, Be...
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
15 years 5 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
TOMACS
2011
139views more  TOMACS 2011»
15 years 1 months ago
The double CFTP method
We consider the problem of the exact simulation of random variables Z that satisfy the distributional identity Z L = V Y + (1 − V )Z, where V ∈ [0, 1] and Y are independent, an...
Luc Devroye, Lancelot F. James
TVLSI
2010
15 years 1 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
INFOCOM
2008
IEEE
16 years 1 months ago
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of toda...
Weirong Jiang, Qingbo Wang, Viktor K. Prasanna