Sciweavers

3156 search results - page 334 / 632
» An address translation simulator
Sort
View
DAC
1999
ACM
15 years 11 months ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
ICCD
1999
IEEE
88views Hardware» more  ICCD 1999»
15 years 11 months ago
TriMedia CPU64 Application Development Environment
The architecture of the TriMedia CPU64 is based on the TM1000 DSPCPU. The original VLIW architecture has been extended with the concepts of vector processing and superoperations. ...
Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndho...
ICDCS
1999
IEEE
15 years 11 months ago
Scalable Processing of Read-Only Transactions in Broadcast Push
Recently, push-based delivery has attracted considerable attention as a means of disseminating information to large client populations in both wired and wireless settings. In this...
Evaggelia Pitoura, Panos K. Chrysanthis
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
15 years 11 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag
VTS
1999
IEEE
83views Hardware» more  VTS 1999»
15 years 11 months ago
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
Philip P. Shirvani, Edward J. McCluskey