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EUROMICRO
1999
IEEE
15 years 11 months ago
The X-MatchLITE FPGA-Based Data Compressor
This paper introduces a hardware amenable algorithm for lossless data compression and a highly integrable architecture which enables Gbit/s compression using contemporary ASIC tec...
Jose Luis Nunez, Claudia Feregrino, Simon Jones, S...
POPL
2000
ACM
15 years 10 months ago
Modular Refinement of Hierarchic Reactive Machines
with existing analysis tools. Modular reasoning principles such as abstraction, compositional refinement, and assume-guarantee reasoning are well understood for architectural hiera...
Rajeev Alur, Radu Grosu
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Efficient BMC for Multi-Clock Systems with Clocked Specifications
- Current industry trends in system design -- multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with...
Malay K. Ganai, Aarti Gupta
ISMVL
2007
IEEE
104views Hardware» more  ISMVL 2007»
16 years 28 days ago
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
Mahsan Amoui, Daniel Große, Mitchell A. Thor...
ENTCS
2006
133views more  ENTCS 2006»
15 years 6 months ago
Linking Semantic Models to Support CSP || B Consistency Checking
Consistency checking in the CSP B approach verifies that an individual controller process, defined using a sequential non-divergent subset of CSP, never calls a B operation outsid...
Neil Evans, Helen Treharne