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» An Experimental Analysis of Parallel
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HPCA
2009
IEEE
16 years 7 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
16 years 7 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
HPCA
2008
IEEE
16 years 7 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...
HPCA
2006
IEEE
16 years 7 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
PLDI
2010
ACM
16 years 4 months ago
Pacer: Proportional Detection of Data Races
Data races indicate serious concurrency bugs such as order, atomicity, and sequential consistency violations. Races are difficult to find and fix, often manifesting only in deploy...
Michael D. Bond, Katherine E. Coons, Kathryn S. Mc...
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