34 search results - page 7 / 7 » An Evaluation of Directory Schemes for Cache Coherence |
153
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ISCA
2000
IEEE
15 years 10 months ago
2000
IEEE
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
157
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ISCA
2000
IEEE
15 years 10 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
164
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MICRO
2010
IEEE
15 years 23 days ago
2010
IEEE
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
159
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MICRO
2010
IEEE
15 years 3 months ago
2010
IEEE
A particularly insidious type of concurrency bug is atomicity violations. While there has been substantial work on automatic detection of atomicity violations, each existing techn...