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» An Evaluation of Current High-Performance Networks
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MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
16 years 10 days ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
CODES
2005
IEEE
15 years 12 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
INFOCOM
2002
IEEE
15 years 11 months ago
Fair Scheduling and Buffer Management in Internet Routers
Abstract—Input buffered switch architecture has become attractive for implementing high performance routers and expanding use of the Internet sees an increasing need for quality ...
Nan Ni, Laxmi N. Bhuyan
CCGRID
2010
IEEE
15 years 6 months ago
FaReS: Fair Resource Scheduling for VMM-Bypass InfiniBand Devices
In order to address the high performance I/O needs of HPC and enterprise applications, modern interconnection fabrics, such as InfiniBand and more recently, 10GigE, rely on network...
Adit Ranadive, Ada Gavrilovska, Karsten Schwan
FGCS
2008
109views more  FGCS 2008»
15 years 6 months ago
Gridification of collaborative audiovisual organizations through the MediaGrid framework
Abstract In this publication, we discuss a use case for employing Grid technology in a media production / distribution environment. This type of environment is faced with the chall...
Bruno Volckaert, Tim Wauters, Marc De Leenheer, Pi...