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ASPLOS
1992
ACM
15 years 10 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
AUSAI
2009
Springer
15 years 10 months ago
Classification of EEG for Affect Recognition: An Adaptive Approach
Research on affective computing is growing rapidly and new applications are being developed more frequently. They use information about the affective/mental states of users to adap...
Omar AlZoubi, Rafael A. Calvo, Ronald H. Stevens
ATVA
2007
Springer
150views Hardware» more  ATVA 2007»
15 years 10 months ago
3-Valued Circuit SAT for STE with Automatic Refinement
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
Orna Grumberg, Assaf Schuster, Avi Yadgar
FCCM
2009
IEEE
115views VLSI» more  FCCM 2009»
15 years 10 months ago
Multi-Core Architecture on FPGA for Large Dictionary String Matching
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
Qingbo Wang, Viktor K. Prasanna
EPS
1995
Springer
15 years 10 months ago
PANIC: A Parallel Evolutionary Rule Based System
PANIC (Parallelism And Neural networks In Classifier systems) is a parallel system to evolve behavioral strategies codified by sets of rules. It integrates several adaptive techni...
Antonella Giani, Fabrizio Baiardi, Antonina Starit...