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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 12 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
JETAI
2007
131views more  JETAI 2007»
15 years 6 months ago
A computational architecture for heterogeneous reasoning
Reasoning, problem solving, indeed the general process of acquiring knowledge, is not an isolated, homogenous affair involving a one agent using a single form of representation, b...
Dave Barker-Plummer, John Etchemendy
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
ICML
1998
IEEE
16 years 7 months ago
RL-TOPS: An Architecture for Modularity and Re-Use in Reinforcement Learning
This paper introduces the RL-TOPs architecture for robot learning, a hybrid system combining teleo-reactive planning and reinforcement learning techniques. The aim of this system ...
Malcolm R. K. Ryan, Mark D. Pendrith
COMPSAC
2008
IEEE
16 years 23 days ago
An Adaptive Software Architecture Model Based on Component-Mismatches Detection and Elimination
Commercial-off-the-shelf components (COTS) are widely reused at present and black-box composition is the unique way to integrate them into the target system. However, various mism...
Shan Tang, Xin Peng, Yiming Lau, Wenyun Zhao, Zhix...