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HPCA
1999
IEEE
15 years 10 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
DAC
2006
ACM
15 years 10 months ago
Refined statistical static timing analysis through
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
EDOC
2008
IEEE
16 years 23 days ago
On Creating Industry-Wide Reference Architectures
Many industries have been developing e-business standards to improve business-to-business interoperability on a mass scale. Most such standards are composed of business data model...
Liming Zhu, Mark Staples, Vladimir Tosic
EDOC
2002
IEEE
15 years 11 months ago
Business Modelling for Component Systems with UML
The EC funded COMBINE Project has the objective of dramatically improving software development productivity by providing a holistic approach to component-based development of Ente...
Sandy Tyndale-Biscoe, Oliver Sims, Bryan Wood, Chr...
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
16 years 11 days ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer