2733 search results - page 289 / 547 » An Architecture for Compressive Imaging |
186
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ISCAS
2003
IEEE
15 years 12 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
177
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VLSID
2000
IEEE
15 years 11 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
154
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ICIP
1999
IEEE
16 years 8 months ago
1999
IEEE
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
178
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ICIP
2009
IEEE
16 years 7 months ago
2009
IEEE
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
327
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CBMS
2006
IEEE
16 years 23 days ago
2006
IEEE
The growing complexity of distributed biomedical application requirements present new challenges to the representation of software architectural analysis and design. This is the c...