2545 search results - page 63 / 509 » An Architectural Discussion on DSPL |
186
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CODES
2011
IEEE
14 years 6 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
142
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DAC
1999
ACM
16 years 7 months ago
1999
ACM
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
140
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FCCM
2006
IEEE
16 years 11 days ago
2006
IEEE
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This...
143
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EURONGI
2004
Springer
15 years 11 months ago
2004
Springer
Abstract. In this paper we present a P2P file-sharing architecture optimized for mobile networks. We discuss the applicability of current P2P techniques for resource access and me...
236
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Publication
This survey paper explains the issues in designing terabit routers and the solutions for them. The discussion includes multi-layer switching, route caching, label switching, and ef...