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» An Architectural Discussion on DSPL
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FMICS
2006
Springer
15 years 10 months ago
Can Saturation Be Parallelised?
Abstract. Symbolic state-space generators are notoriously hard to parallelise. However, the Saturation algorithm implemented in the SMART verification tool differs from other seque...
Jonathan Ezekiel, Gerald Lüttgen, Radu Simini...
FPGA
2006
ACM
125views FPGA» more  FPGA 2006»
15 years 10 months ago
Armada: timing-driven pipeline-aware routing for FPGAs
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
Kenneth Eguro, Scott Hauck
FPL
2006
Springer
120views Hardware» more  FPL 2006»
15 years 10 months ago
Regular Expression Software Deceleration for Intrusion Detection Systems
The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources. Regular expressions...
Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jun...
CAV
2001
Springer
80views Hardware» more  CAV 2001»
15 years 10 months ago
Transformation-Based Verification Using Generalized Retiming
In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based...
Andreas Kuehlmann, Jason Baumgartner
CCGRID
2001
IEEE
15 years 10 months ago
Compute Power Market: Towards a Market-Oriented Grid
The Compute Power Market (CPM) is a market-based resource management and job scheduling system for grid computing on Internet-wide computational resources, particularly low-end pe...
Rajkumar Buyya, Sudharshan Vazhkudai