2545 search results - page 353 / 509 » An Architectural Discussion on DSPL |
192
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EDBT
2006
ACM
16 years 6 months ago
2006
ACM
In [12] we introduce a novel architecture for data processing, based on a functional fusion between a data and a computation layer. In this demo we show how this architecture is le...
159
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ICCD
2006
IEEE
16 years 3 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
186
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CC
2010
Springer
16 years 1 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
180
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ARC
2009
Springer
16 years 1 months ago
2009
Springer
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
173
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TPHOL
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract. Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory mode...