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» An Architectural Discussion on DSPL
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INFOCOM
2005
IEEE
16 years 7 days ago
A cost-based analysis of overlay routing geometries
— In this paper, we propose a cost-based model to evaluate the resources that each node has to contribute for participating in an overlay network. Such a cost model allows to gau...
Nicolas Christin, John Chuang
IPPS
2005
IEEE
16 years 7 days ago
User Transparent Parallel Processing of the 2004 NIST TRECVID Data Set
The Parallel-Horus framework, developed at the University of Amsterdam, is a unique software architecture that allows non-expert parallel programmers to develop fully sequential m...
Frank J. Seinstra, Cees Snoek, Dennis Koelma, Jan-...
LCN
2005
IEEE
16 years 6 days ago
Network Management Challenges for Next Generation Networks
Generally, current network management technologies follow two approaches: ITU-T’s recommendations for Telecommunication Management Network (TMN) and IETF’s Simple Network Mana...
Mo Li, Kumbesan Sandrasegaran
MICRO
2005
IEEE
140views Hardware» more  MICRO 2005»
16 years 6 days ago
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen,...
MSS
2005
IEEE
110views Hardware» more  MSS 2005»
16 years 6 days ago
Fermilab's Multi-Petabyte Scalable Mass Storage System
Fermilab provides a multi-Petabyte scale mass storage system for High Energy Physics (HEP) Experiments and other scientific endeavors. We describe the scalability aspects of the h...
Gene Oleynik, Bonnie Alcorn, Wayne Baisley, Jon Ba...