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» An Architectural Design for Digital Objects
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DAC
2006
ACM
16 years 7 months ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
16 years 6 months ago
IEEE 1394a_2000 Physical Layer ASIC
CN4011A is IEEE 1394a_2000 standard Compliant Physical Layer ASIC. It is a 0.18um mixed-signal ASIC incorporating three analog ports, PLL, reference generator for analog along wit...
Ranjit Yashwante, Bhalchandra Jahagirdar
PETRA
2009
ACM
16 years 1 months ago
Towards a social fabric for pervasive assistive environments
The digital divide refers to a lack of technological access, part of which involves exclusion from a blooming arena of social interaction. People without mobile phones or PCs cann...
Clare Owens, David E. Millard, Andrew Stanford-Cla...
DATE
2008
IEEE
148views Hardware» more  DATE 2008»
16 years 29 days ago
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications
Stream processing applications such as image signal processing demand high throughput. However, customers increasingly demand runtime flexibility in their designs, which cannot b...
Mark Muir, Tughrul Arslan, Iain Lindsay
ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
16 years 23 days ago
On-Line Histogram Equalization for Flash ADC
— We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.3...
Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire