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» An Architectural Design for Digital Objects
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DAC
2005
ACM
15 years 8 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
DAC
2008
ACM
16 years 7 months ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel
EUROGRAPHICS
2010
Eurographics
16 years 3 months ago
Reinterpretable Imager: Towards Variable Post-Capture Space, Angle and Time Resolution in Photography
We describe a novel multiplexing approach to achieve tradeoffs in space, angle and time resolution in photography. We explore the problem of mapping useful subsets of time-varying...
Amit Agrawal, Ashok Veeraraghavan, Ramesh Raskar
JCDL
2009
ACM
115views Education» more  JCDL 2009»
16 years 1 months ago
Using timed-release cryptography to mitigate the preservation risk of embargo periods
Due to temporary access restrictions, embargoed data cannot be refreshed to unlimited parties during the embargo time interval. A solution to mitigate the risk of data loss has be...
Rabia Haq, Michael L. Nelson
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
16 years 25 days ago
Multiple-Width Bus Partitioning Approach to Datapath Synthesis
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
Arash Ahmadi, Mark Zwolinski