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ICS
1999
Tsinghua U.
15 years 11 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
15 years 11 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
SIGSOFT
2003
ACM
15 years 12 months ago
Modeling and validation of service-oriented architectures: application vs. style
Most applications developed today rely on a given middleware platform which governs the interaction between components, the access to resources, etc. To decide, which platform is ...
Luciano Baresi, Reiko Heckel, Sebastian Thöne...
ACMSE
2011
ACM
14 years 6 months ago
Targeting FPGA-based processors for an implementation-driven compiler construction course
This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the ...
D. Brian Larkins, William M. Jones
CIG
2006
IEEE
16 years 22 days ago
A Behavior-Based Architecture for Realistic Autonomous Ship Control
— Game environments provide a good domain for serious simulations such as those used in training Navy conning officers. Currently, a typical training scenario requires multiple ...
Adam Olenderski, Monica N. Nicolescu, Sushil J. Lo...