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DAC
2010
ACM
15 years 6 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
RTCSA
2003
IEEE
15 years 12 months ago
Introducing Temporal Analyzability Late in the Lifecycle of Complex Real-Time Systems
Many industrial real-time systems have evolved over a long period of time and were initially so simple that it was possible to predict consequences of adding new functionality by c...
Anders Wall, Johan Andersson, Jonas Neander, Chris...
ECBS
2008
IEEE
116views Hardware» more  ECBS 2008»
16 years 1 months ago
CiCUTS: Combining System Execution Modeling Tools with Continuous Integration Environments
System execution modeling (SEM) tools provide an effective means to evaluate the quality of service (QoS) of enterprise distributed real-time and embedded (DRE) systems. SEM tools...
James H. Hill, Douglas C. Schmidt, Adam A. Porter,...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
16 years 9 days ago
Rapid Generation of Thermal-Safe Test Schedules
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...
Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu...
INTEGRATION
2007
98views more  INTEGRATION 2007»
15 years 6 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...