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DAC
2008
ACM
16 years 7 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
DAC
2008
ACM
16 years 7 months ago
Type-matching clock tree for zero skew clock gating
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-...
DAC
2007
ACM
16 years 7 months ago
Implicitly Parallel Programming Models for Thousand-Core Microprocessors
This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly paralle...
Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H....
DAC
2007
ACM
16 years 7 months ago
Design Methodology for Pipelined Heterogeneous Multiprocessor System
Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processo...
Seng Lin Shee, Sri Parameswaran
DAC
1998
ACM
16 years 7 months ago
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs
In this paper we present a new global router appropriate for Multichip Module MCM and dense Printed Circuit Board PCB design, which utilizes a hybrid of the classical rip-up and r...
Jason Cong, Patrick H. Madden
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