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ICCAD
1999
IEEE
119views Hardware» more  ICCAD 1999»
15 years 11 months ago
Factoring logic functions using graph partitioning
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
Martin Charles Golumbic, Aviad Mintz
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
15 years 11 months ago
Regularity extraction via clan-based structural circuit decomposition
Identifying repeating structural regularities in circuits allows the minimization of synthesis, optimization, and layout e orts. We introduce in this paper a novel method for ident...
Soha Hassoun, Carolyn McCreary
ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
15 years 11 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
15 years 11 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
ICCV
1999
IEEE
15 years 11 months ago
Learning Low-Level Vision
We describe a learning-based method for low-level vision problems--estimating scenes from images. We generate a synthetic world of scenes and their corresponding rendered images, m...
William T. Freeman, Egon C. Pasztor
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