The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstractio...
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented ...
Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. ...
This paper reports on a specific food and agribusiness industry project, employing new technological capabilities to better transfer expert knowledge. Knowledge transfer and techn...
Deformable 3–D models can be represented either as explicit or implicit surfaces. Explicit surfaces, such as triangulations or wire-frame models, are widely accepted in the Comp...