A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
This paper is a sequel of previous work, in which we have studied the traffic management problem in UMTS. The main objective was to improve the spectral efficiency of cellular netw...
Larissa Popova, Wolfgang H. Gerstacker, Wolfgang K...
Basic message processing tasks, such as wellformedness checking and grammar validation, can be off-loaded from the service providers' own infrastructures. To enable effective...
—Recently, there has been a growing interest of using network coding to improve the performance of wireless networks, for example, authors of [1] proposed the practical wireless ...
As multi/many core processors become prevalent, programming language is important in constructing efficient parallel applications. In this work, we build a multithreaded video min...
Wenlong Li, Eric Li, Ran Meng, Tao Wang, Carole Du...