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HPCA
2011
IEEE
14 years 10 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
PDP
2011
IEEE
14 years 10 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
HPCA
2012
IEEE
14 years 2 months ago
SCD: A scalable coherence directory with flexible sharer set encoding
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond...
Daniel Sanchez, Christos Kozyrakis
ICS
2003
Tsinghua U.
15 years 11 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
CIVR
2009
Springer
253views Image Analysis» more  CIVR 2009»
16 years 1 months ago
Spatial extensions to bag of visual words
The Bag of Visual Words (BoV) paradigm has successfully been applied to image content analysis tasks such as image classification and object detection. The basic BoV approach ove...
Ville Viitaniemi, Jorma Laaksonen
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