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CF
2005
ACM
15 years 8 months ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
DAC
2006
ACM
15 years 8 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
CONEXT
2005
ACM
15 years 8 months ago
Achieving sub-50 milliseconds recovery upon BGP peering link failures
We first show by measurements that BGP peering links fail as frequently as intradomain links and usually for short periods of time. We propose a new fast-reroute technique where ...
Olivier Bonaventure, Clarence Filsfils, Pierre Fra...
PKC
2010
Springer
126views Cryptology» more  PKC 2010»
15 years 8 months ago
Implicit Factoring with Shared Most Significant and Middle Bits
We study the problem of integer factoring given implicit information of a special kind. The problem is as follows: let N1 = p1q1 and N2 = p2q2 be two RSA moduli of same bit-size, w...
Jean-Charles Faugère, Raphaël Marinier...
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
15 years 8 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
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