8903 search results - page 1527 / 1781 » Alternative |
181
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ISCA
2005
IEEE
16 years 6 days ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
153
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ISCA
2005
IEEE
16 years 6 days ago
2005
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have prim...
221
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ISPASS
2005
IEEE
16 years 6 days ago
2005
IEEE
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
170
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MICRO
2005
IEEE
16 years 6 days ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
167
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MICRO
2005
IEEE
16 years 6 days ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...