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» Algorithms for Interface Synthesis
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DAC
2009
ACM
16 years 7 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ICDCS
2003
IEEE
15 years 12 months ago
Enhancing The Fault-Tolerance of Nonmasking Programs
In this paper, we focus on automated techniques to enhance the fault-tolerance of a nonmasking fault-tolerant program to masking. A masking program continually satisfies its spec...
Sandeep S. Kulkarni, Ali Ebnenasir
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
15 years 10 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
EMSOFT
2006
Springer
15 years 10 months ago
Incremental schedulability analysis of hierarchical real-time components
Embedded systems are complex as a whole but consist of smaller independent modules minimally interacting with each other. This structure makes embedded systems amenable to composi...
Arvind Easwaran, Insik Shin, Oleg Sokolsky, Insup ...
BMCBI
2005
124views more  BMCBI 2005»
15 years 6 months ago
ErmineJ: Tool for functional analysis of gene expression data sets
Background: It is common for the results of a microarray study to be analyzed in the context of biologically-motivated groups of genes such as pathways or Gene Ontology categories...
Homin K. Lee, William Braynen, Kiran Keshav, Paul ...