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» Algorithms for Interface Synthesis
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ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
15 years 11 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
ISSS
1997
IEEE
142views Hardware» more  ISSS 1997»
15 years 11 months ago
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination
- An approach for broadband modem FIR filter design optimization is presented. It addresses the minimization of the number of addersubtractors used in the hardware implementation o...
Robert Pasko, Patrick Schaumont, Veerle Derudder, ...
ISLPED
1997
ACM
96views Hardware» more  ISLPED 1997»
15 years 11 months ago
Re-mapping for low power under tight timing constraints
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
DAC
1996
ACM
15 years 10 months ago
Delay Minimal Decomposition of Multiplexers in Technology Mapping
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
Shashidhar Thakur, D. F. Wong, Shankar Krishnamoor...
DATE
2009
IEEE
107views Hardware» more  DATE 2009»
15 years 10 months ago
Sequential logic rectifications with approximate SPFDs
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, R...