Sciweavers

3456 search results - page 296 / 692
» Algorithms for Interface Synthesis
Sort
View
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
16 years 1 months ago
Accurate and scalable reliability analysis of logic circuits
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...
Mihir R. Choudhury, Kartik Mohanram
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
16 years 1 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
GECCO
2007
Springer
166views Optimization» more  GECCO 2007»
16 years 25 days ago
Scalable estimation-of-distribution program evolution
I present a new estimation-of-distribution approach to program evolution where distributions are not estimated over the entire space of programs. Rather, a novel representationbui...
Moshe Looks
ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
16 years 22 days ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
IPPS
2006
IEEE
16 years 21 days ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...